The present invention generally relates to a pulse signal delay circuit, and, more particularly, to a pulse signal delay circuit including a plurality of delay elements.
In general, a pulse signal delay circuit includes a plurality of delay elements connected in series. In a CMOS semiconductor device, a delay element is formed by an inverter comprising a P-channel MOS transistor and an N-channel MOS transistor. A selector is preferably connected to a plurality of delay elements and selects one of delay outputs from the plurality of delay elements. Accordingly, the delay time of an input signal is determined. A comparator may be used instead of the inverter. However, in order to change the delay time in each of a plurality of input pulse signals, the conventional delay circuit requires the same number of delay circuits and selectors, as the input pulse signals. Hence, the area of the delay circuit is quite large.
The delay circuit may be formed by a plurality of series connected D type flip-flops (D-FF) each of which operates in synchronism with a clock signal. In this case, a high-speed clock is required to finely set the delay time of the clock signal. In fact, it is difficult to supply the high-speed clock signal and to prepare a D-FF that operates stably in synchronism with the high-speed clock signal.
It is an object of the present invention to provide a pulse signal delay circuit having a reduced circuit area.
In one aspect of the present invention, a pulse delay circuit provided that includes a delay circuit, a plurality of selectors and a plurality of synchronous circuits. The delay circuit includes a plurality of series connected delay elements for delaying a clock signal and generating a plurality of delay clock signals. Each of the plurality of selectors is connected to the plurality of delay elements and selects one of the plurality of the delay clock signals in accordance with an associated selection signal. The plurality of synchronous circuits are connected to the plurality of selectors, respectively. The plurality of synchronous circuits receive pulse signals and the selected delay clock signals and generate a plurality of synchronous pulse signals that are synchronized with the selected delay clock signals, respectively.
In another aspect of the present invention, a pulse signal control circuit is provided that includes a first synchronous circuit for receiving an input signal and a clock signal and generating a first synchronous input signal that is synchronized with the clock signal. A waveform shaping circuit waveform-shapes the first synchronous input signal and generates a waveform-shaped input signal. A plurality of second synchronous circuits receive a plurality of input pulse signals and the clock signal and generate a plurality of second synchronous input pulse signals that are synchronized with the clock signal. A delay circuit includes a plurality of delay elements for delaying the clock signal and generating a plurality of delay clock signals. Each of a plurality of selectors selects one of the plurality of delay clock signals in accordance with an associated selection signal. A plurality of third synchronous circuits receive the plurality of second synchronous input pulse signals and the selected delay clock signals and generate a plurality of third synchronous input pulse signals that are synchronized with the selected delay clock signals, respectively. A plurality of logic circuits receive the waveform-shaped input signal and the plurality of third synchronous input pulse signals and generate a plurality of pulse signals that are synchronized with the waveform-shaped input signal.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.